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Features
* High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture
- 123 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Non-volatile Program and Data Memories - 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny261/461/861) Endurance: 10,000 Write/Erase Cycles - 128/256/512 Bytes In-System Programmable EEPROM (ATtiny261/461/861) Endurance: 100,000 Write/Erase Cycles - 128/256/512 Bytes Internal SRAM (ATtiny261/461/861) - Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features - 8/16-bit Timer/Counter with Prescaler and Two PWM Channels - 8/10-bit High Speed Timer/Counter with Separate Prescaler 3 High Frequency PWM Outputs with Separate Output Compare Registers Programmable Dead Time Generator - Universal Serial Interface with Start Condition Detector - 10-bit ADC 11 Single Ended Channels 16 Differential ADC Channel Pairs 15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x) - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Low Power Idle, ADC Noise Reduction, and Power-down Modes - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated Oscillator I/O and Packages - 16 Programmable I/O Lines - 20-pin PDIP, 20-pin SOIC and 32-pad MLF Operating Voltage: - 1.8 - 5.5V for ATtiny261V/461V/861V - 2.7 - 5.5V for ATtiny261/461/861 Speed Grade: - ATtiny261V/461V/861V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V - ATtiny261/461/861: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption - Active Mode: 1 MHz, 1.8V: 380A - Power-down Mode: 0.1A at 1.8V
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8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny261/V ATtiny461/V ATtiny861/V Preliminary Summary
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1. Pin Configurations
Figure 1-1. Pinout ATtiny261/461/861
PDIP/SOIC
(MOSI/DI/SDA/OC1A/PCINT8) PB0 (MISO/DO/OC1A/PCINT9) PB1 (SCK/USCK/SCL/OC1B/PCINT10) PB2 (OC1B/PCINT11) PB3 VCC GND (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0/DI/SDA/PCINT0) PA1 (ADC1/DO/PCINT1) PA2 (ADC2/INT1/USCK/SCL/PCINT2) PA3 (AREF/PCINT3) AGND AVCC PA4 (ADC3/ICP0/PCINT4) PA5 (ADC4/AIN2/PCINT5) PA6 (ADC5/AIN0/PCINT6) PA7 (ADC6/AIN1/PCINT7)
32 31 30 29 28 27 26 25
PB2 (SCK/USCK/SCL/OC1B/PCINT10) PB1 (MISO/DO/OC1A/PCINT9) PB0 (MOSI/DI/SDA/OC1A/PCINT8) NC NC NC PA0 (ADC0/DI/SDA/PCINT0) PA1 (ADC1/DO/PCINT1)
NC (OC1B/PCINT11) PB3 NC VCC GND NC (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
1 2 3 4 5 6 7 8
QFN/MLF
24 23 22 21 20 19 18 17
NC PA2 (ADC2/INT1/USCK/SCL/PCINT2) PA3 (AREF/PCINT3) AGND NC NC AVCC PA4 (ADC3/ICP0/PCINT4)
Note:
The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.
1.1
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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NC (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 NC (ADC6/AIN1/PCINT7) PA7 (ADC5/AIN0/PCINT6) PA6 (ADC4/AIN2/PCINT5) PA5 NC
9 10 11 12 13 14 15 16
ATtiny261/461/861
2. Overview
The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
GND VCC
Watchdog Timer Watchdog Oscillator
Power Supervision POR / BOD & RESET
debugWIRE
PROGRAM LOGIC
Oscillator Circuits / Clock Generation
Flash
SRAM
CPU EEPROM
AVCC AGND AREF
Timer/Counter0
DATABUS
Timer/Counter1
A/D Conv.
USI
Analog Comp.
Internal Bandgap
3
11
PORT B (8)
PORT A (8)
RESET XTAL[1..2] PB[0..7] PA[0..7]
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny261/461/861 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
2.2
2.2.1
Pin Descriptions
VCC Supply voltage.
2.2.2
GND Ground.
2.2.3
AVCC Analog supply voltage.
2.2.4
AGND Analog ground.
2.2.5
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny261/461/861 as listed on page 65.
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2.2.6 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny261/461/861 as listed on page 61. 2.2.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 23-3 on page 189. Shorter pulses are not guaranteed to generate a reset.
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3. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
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4. Register Summary
Address
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
SREG SPH SPL Reserved GIMSK GIFR TIMSK TIFR SPMCSR PRR MCUCR MCUSR TCCR0B TCNT0L OSCCAL TCCR1A TCCR1B TCNT1 OCR1A OCR1B OCR1C OCR1D PLLCSR CLKPR TCCR1C TCCR1D TC1H DT1 PCMSK0 PCMSK1 WDTCR DWDR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB TCCR0A TCNT0H OCR0A OCR0B USIPP USIBR USIDR USISR USICR GPIOR2 GPIOR1 GPIOR0 ACSRB ACSRA ADMUX ADCSRA ADCH ADCL ADCSRB DIDR1 DIDR0 TCCR1E
Bit 7
I - SP7 INT1 INTF1 OCIE1D OCF1D - - - -
Bit 6
T - SP6 INT0 INTF0 OCIE1A OCF1A - PUD - -
Bit 5
H - SP5 PCIE1 PCIF OCIE1B OCF1B - SE - -
Bit 4
S - SP4 - PCIE0 - OCIE0A OCF0A CTPB SM1 - TSM
Bit 3
V - SP3 - - OCIE0B OCF0B RFLB PRTIM1 SM0 WDRF PSR0
Bit 2
N SP10 SP2 - - TOIE1 TOV1 PGWRT PRTIM0 - BORF CS02
Bit 1
Z SP9 SP1 - - TOIE0 TOV0 PGERS PRUSI ISC01 EXTRF CS01
Bit 0
C SP8 SP0 - - TICIE0 ICF0 SPMEN PRADC ISC00 PORF CS00
Page
page 9 page 12 page 12 page 51 page 51 page 86, page 123 page 87, page 124 page 166 page 35 page 37, page 68, page 50 page 44, page 70 page 85 page 32
Timer/Counter0 Counter Register Low Byte Oscillator Calibration Register COM1A1 PWM1X COM1A0 PSR1 COM1B1 DTPS11 COM1B0 DTPS10 FOC1A CS13 FOC1B CS12 PWM1A CS11 PWM1B CS10
page 113 page 166 page 121 page 121 page 122 page 122 page 123
Timer/Counter1 Counter Register Timer/Counter1 Output Compare Register A Timer/Counter1 Output Compare Register B Timer/Counter1 Output Compare Register C Timer/Counter1 Output Compare Register D LSM CLKPCE COM1A1S FPIE1 DT1H3 PCINT7 PCINT15 WDIF COM1A0S FPEN1 DT1H2 PCINT6 PCINT14 WDIE COM1B1S FPNC1 DT1H1 PCINT5 PCINT13 WDP3 COM1B0S FPES1 DT1H0 PCINT4 PCINT12 WDCE CLKPS3 COM1D1 FPAC1 DT1L3 PCINT3 PCINT11 WDE PCKE CLKPS2 COM1D0 FPF1 DT1L2 PCINT2 PCINT10 WDP2 PLLE CLKPS1 FOC1D WGM11 TC19 DT1L1 PCINT1 PCINT9 WDP1 PLOCK CLKPS0 PWM1D WGM10 TC18 DT1L0 PCINT0 PCINT8 WDP0 EEAR8 EEAR7 - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 TCW0 EEAR6 - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 ICEN0 EEAR5 EEPM1 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 ICNC0 EEAR4 EEPM0 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 ICES0 EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 ACIC0 EEAR2 EEMPE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 EEAR1 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 WGM00 EEPROM Data Register
page 89 page 32 page 117 page 119 page 121 page 124 page 52 page 52 page 44 page 35 page 21 page 21 page 22 page 22 page 68 page 68 page 68 page 68 page 68 page 68 page 84 page 85 page 85 page 85
DWDR[7:0]
Timer/Counter0 Counter Register High Byte Timer/Counter0 Output Compare Register A Timer/Counter0 Output Compare Register B USIPOS USI Buffer Register USI Data Register USISIF USISIE USIOIF USIOIE USIPF USIWM1 USIDC USIWM0 USICNT3 USICS1 USICNT2 USICS0 USICNT1 USICLK USICNT0 USITC
page 137 page 134 page 133 page 134 page 135 page 23 page 23 page 23
General Purpose I/O Register 2 General Purpose I/O Register 1 General Purpose I/O Register 0 HSEL ACD REFS1 ADEN HLEV ACBG REFS0 ADSC ACO ADLAR ADATE ACI MUX4 ADIF ACIE MUX3 ADIE ACM2 ACME MUX2 ADPS2 ACM1 ACIS1 MUX1 ADPS1 ACM0 ACIS0 MUX0 ADPS0
page 141 page 138 page 154 page 157 page 158 page 158
ADC Data Register High Byte ADC Data Register Low Byte BIN ADC10D ADC6D - GSEL ADC9D ADC5D ADC8D ADC4D OC1OE5 REFS2 ADC7D ADC3D OC1OE4 AREFD OC1OE3 ADC2D OC1OE2 ADC1D OC1OE1 ADC0D OC1OE0 MUX5 ADTS2 ADTS1 ADTS0
page 158 page 160 page 160 page 120
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Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
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5. Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7)
BRANCH INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
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Mnemonics
ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH
Operands
Rd Rd Rd s s Rr, b Rd, b Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear
Description
Rotate Right Through Carry
Operation
Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (z) R1:R0 Rd P P Rr STACK Rr Rd STACK
Flags
Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A
Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only
MCU CONTROL INSTRUCTIONS None None None
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6. Ordering Information
6.1 ATtiny261
Speed (MHz)(3) 10 Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny261V-10MU ATtiny261V-10PU ATtiny261V-10SU ATtiny261-20MU ATtiny261-20PU ATtiny261-20SU Package(1) 32M1-A 20P3 20S2 32M1-A 20P3 20S2 Operational Range Industrial (-40C to 85C)
20 Notes:
2.7 - 5.5V
Industrial (-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 187
Package Type 32M1-A 20P3 20S2 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
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6.2
ATtiny461
Speed (MHz)(3) 10 Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny461V-10MU ATtiny461V-10PU ATtiny461V-10SU ATtiny461-20MU ATTINY461-20PU ATtiny461-20SU Package(1) 32M1-A 20P3 20S2 32M1-A 20P3 20S2 Operational Range Industrial (-40C to 85C)
20 Notes:
2.7 - 5.5V
Industrial (-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 187
Package Type 32M1-A 20P3 20S2 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
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ATtiny261/461/861
6.3 ATtiny861
Speed (MHz)(3) 10 Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny861V-10MU ATtiny861V-10PU ATtiny861V-10SU ATtiny861-20MU ATtiny861-20PU ATtiny861-20SU Package(1) 32M1-A 20P3 20S2 32M1-A 20P3 20S2 Operational Range Industrial (-40C to 85C)
20 Notes:
2.7 - 5.5V
Industrial (-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 187
Package Type 32M1-A 20P3 20S2 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
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7. Packaging Information
7.1 32M1-A
D D1
1 2 3
0
Pin 1 ID E1 E
SIDE VIEW
TOP VIEW
A2
A3 A1
K
P D2
A
0.08 C
COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.80 - - NOM 0.90 0.02 0.65 0.20 REF 0.18 0.23 5.00 BSC 4.75 BSC 2.95 3.10 5.00 BSC 4.75BSC 2.95 3.10 0.50 BSC 0.30 - - 0.20 - 0.40 - - 0.50 0.60 o 12 - 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTE
SYMBOL A
P
Pin #1 Notch (0.20 R)
1 2 3
A1 A2 A3 E2 b
K
D D1 D2 E
b
e
L
E1 E2 e L P
BOTTOM VIEW
0
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. K
8/19/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. D
R
14
ATtiny261/461/861
2588BS-AVR-11/06
ATtiny261/461/861
7.2 20P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 25.493 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 25.984 8.255 7.112 0.559 1.551 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
1/12/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. C
R
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2588BS-AVR-11/06
7.3
20S2
16
ATtiny261/461/861
2588BS-AVR-11/06
ATtiny261/461/861
8. Errata
8.1 Errata ATtiny261
The revision letter in this section refers to the revision of the ATtiny261 device. 8.1.1 Rev A No known errata.
8.2
Errata ATtiny461
The revision letter in this section refers to the revision of the ATtiny461 device.
8.2.1
Rev B Yield improvement. No known errata.
8.2.2
Rev A No known errata.
8.3
Errata ATtiny861
The revision letter in this section refers to the revision of the ATtiny861 device.
8.3.1
Rev B No known errata.
8.3.2
Rev A Not sampled.
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2588BS-AVR-11/06
9. Datasheet Revision History
9.1 Rev. 2588A - 11/06
1. 2. Updated "Ordering Information" on page 222. Updated "Packaging Information" on page 225.
9.2
Rev. 2588A - 10/06
1. Initial Revision.
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ATtiny261/461/861
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